3-3 3-3 features ? microprocessor compatible control inputs ? on chip control memory and address decoding ? row addressing ? master reset ? 32 crosspoint switches in 8 x 4 array ? 5.0v to 15.0v operation ? low crosstalk between switches ? low on resistance: 90 w (typ.) at 13v ? matched switch characteristics ? switches frequencies up to 40mhz applications ? pabx and key sytems ? data acquisition systems ? test equipment/instrumentation ? analog/digital multiplexers description the MT8804a is a cmos/lsi 8 x 4 analog switch array incorporating control memory (32 bits), deco- der and digital logic level converters. this circuit has digitally controlled analog switches having very low on resistance and very low off leakage current. switches will operate with analog signals at frequencies to 40 mhz and up to 15.0vp-p. a high on the master reset input switches all channels off and clears the memory. this device is ideal for crosspoint switching applications. ordering information MT8804ac 24 pin ceramic dip MT8804ae 24 pin plastic dip MT8804ap 28 pin plcc -40 to 85c figure 1 - functional block diagram 3 to 8 decoder latches 8 x 4 switch array 11 832 ae d0 d1 d2 d3 vdd vee vss a0 a1 a2 mr ji i/o (i=0-3) li i/o (i=0-7) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? issue 2 october 1989 MT8804a 8 x 4 analog switch array cmos
MT8804a cmos 3-4 figure 2 - pin connections * plastic dip and cerdip only pin description pin #* name description 1-3 l2-l0 l2-l0 analog lines (inputs/outputs): these are connected to the l2-l0 columns of the switch array. 4d0 d0 data (input) : active high. 5j0 j0 analog junctor (input/output): this is connected to the j0 row of the switch array. 6di di data (input). active high. 7j1 j1 analog junctor (input/output): this is connected to the j1 row of the switch array. 8d2 d2 data (input) : active high. 9j2 j2 analog junctor (input/output): this is connected to the j2 row of the switch array. 10 d3 d3 data (input) : active high. 11 j3 j3 analog junctor (input/output): this is connected to the j3 row of the switch array. 12 v ss digital ground reference. 13 v ee negative power supply. 14-16 a0-a2 a0-a2 address lines (inputs) . 17 ae address enable/strobe (input) : enables function selected by address and data. address must be stable before ae goes high and d0-d3 must be stable on the falling edge of the ae. active high. 18 mr master reset (input): this is used to turn off all switches. active high. 19-23 l7-l3 l7-l3 analog lines (inputs/outputs): these are connected to the l7-l3 columns of the switch array. 24 v dd positive power supply. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 l2 l1 l0 d0 j0 d1 j1 d2 j2 d3 j3 vss vdd l3 l4 l5 l6 l7 mr ae a2 a1 a0 vee 28 pin plcc 24 pin cerdip/plastic dip 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 n c l5 l6 l7 mr ae a2 nc nc d0 j0 d1 j1 d2 j2 a 1 3 2 1 2 8 2 7 2 6 1 2 1 3 1 4 1 5 1 6 1 7 1 8 l 0 l 1 l 2 v d d l 3 l 4 d 3 j 3 v s s v e e a 0 n c
cmos MT8804a 3-5 functional description the MT8804a is a cmos/lsi 8 x 4 analog switch array incorporating an 8 x 4 analog switch array, address decoder, control memory, and digital logic level converter . the analog switch array is arranged in 8 rows and 4 columns. the row input/outputs are referred to as lines (l0-l7) and the column input/outputs as junctors (j0-j3). the crosspoint analog switches interconnect the lines and junctors when turned on and provide a high degree of isolation when turned off. interchannel crosstalk is minimal despite the high density of the analog switch array. the control memory of the MT8804a can be treated as an 8 word by 4 bit random access memory. the 8 words are selected by the address (a0-a2) inputs through the on chip address decoder. data is presented to the memory via the four data inputs (d0-d3). this data is asynchronously written into the control memory whenever the address enable (ae) input is high. a high level written into a memory cell turns the corresponding crosspoint switch on while a low level causes the crosspoint to turn off. only the crosspoint switches corresponding to the addressed memory word are affected when data is written into the memory. the remaining switches retain their previous states. by establishing appropriate patterns in the control memory, any combination of lines and junctors may be interconnected. a high level on the master reset (mr) input returns all memory locations to a low level and turns all crosspoint switches off effectively isolating the lines from the junctors. the digital logic level converters allow the digital input levels to differ from limits of the analog levels switched through the array. for example, with figure 3 - on resistance vs. temperature (input signal voltage=supply voltage/2) v dd =5v, v ss =0v and v ee =-6v, the control inputs can be driven by a 5v system while the analog voltages through the crosspoint switches can swing from +5v to -6v. figure 4 - on resistance vs. input signal voltage figure 5 - 8 x 8 analog/digital switch 8x8 analog/digital switch two MT8804s configured as shown, implement an 8 x 8 analog/digital switch. the switch capacity can be expanded to an m x n array of inputs/ outputs. expansion in the m dimension is as shown with the MT8804a lines (l0-l7) commoned. expansion in the n dimension is accomplished by replicating the circuit shown and connecting the MT8804a junctors (j0-j3) in common. the address and data control inputs of the MT8804as can be connected in common for any size and switch provided that the address enable (ae) inputs are driven individually. a particular signal path is connected by setting up the appropriate signals or the address and data lines and taking the corresponding address enable input high. the master reset (mr), when taken high, disconnects all signal paths.
MT8804a cmos 3-6 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are at ambient temperature (25c). ? typical figures are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ee unless otherwise stated . parameter symbol min max units 1 supply voltage v dd- v ss v dd- v ee v ss- v ee -0.3 -0.3 -0.3 16 16 16 v v v 2 analog input voltage v ina v ee -0.3 v dd +0.3 v 3 digital input voltage v in v ss -0.3 v dd +0.3 v 4 current on any logic pin i 10 ma 5 storage temperature t s -65 +150 c 6 package power dissipation plastic dip cerdip p d p d 0.6 1.2 w w recommended operating conditions - voltages are with respect to v ee unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t o -40 25 85 c 2 supply voltage v dd -v ss v dd -v ee v ss -v ee 5 5 0 5 10 5 15 15 10 v v v 3 analog input voltage v ina v ee v dd v 4 digital input voltage v in v ss v dd v dc electrical characteristics ? - voltages are with respect to v ee =v ss =0v. characteristics sym min typ ? max units test conditions 1 quiescent supply current i dd 1100 av dd =15v. all digital inputs at v in =v ss or v dd 2 off-state leakage current (any line to any junctor) i off 0.1 500 na v dd =13v, switch is off iv ji - v lj i = v dd - v ee 3 input logic 0 level v il 3.0 1.5 v v v dd =10v v dd =5v v ina =v dd through 1k w 4 input logic 1 level v ih 7.0 3.5 v v v dd =10v v dd =5v v ina =v dd through 1k w 5 maximum current through crosspoint switch i max 8.0 ma v dd =13v dc electrical characteristics - switch resistance - v dc is the external dc offset applied at the analog i/o pins. characteristics sym 25c 70c 85c units test conditions min typ max typ typ 1 on-state v dd =13v resistance v dd =10v v dd = 5v r on 60 90 105 290 108 160 650 105 120 320 110 125 325 w w w v ss =v ee =0v,v dc =v dd /2, iv ji - v lj i = 0.6v 2 difference in on-state resistance between two switches v dd =13v v dd =10v d r on 20 30 20 30 20 30 w w v ss =v ee =0v,v dc =v dd /2, iv ji - v lj i = 0.6v
cmos MT8804a 3-7 ? ac electrical characteristics are at ambient temperature (25c). ? typical figures are for design aid only; not guaranteed and not subject to production testing. ? ac electrical characteristics are at ambient temperature (25c). ? typical figures are for design aid only; not guaranteed and not subject to production testing. note 1 r l = 10k w , c l =50pf note 2 r l = 1k w , c l =50pf digital input rise time (tr) and fall time (tf) = 5ns. ac electrical characteristics ? - crosspoint performance -v dc is the external dc offset applied at the analog i/o pins. voltages are with respect to v dd =10v, v ss =v ee =0v unless otherwise stated. characteristics sym min typ ? max units test conditions 1 switch line capacitance c is 5pf 2 switch junctor capacitance c os 20 pf 3 feedthrough capacitance c i 0.2 pf 4 frequency response channel on 20log(v out / v ina ) = -3db f 3db 40 mhz switch is on; v dc =5v, v ina =5vpp sinewave f= 1khz; r l = 1k w 5 total harmonic distortion v dd =15v/v dc =7.5v v dd =10v/v dc =5v v dd =5v/v dc =2.5v thd 0.1 0.2 1.0 % % % switch is on; v ee= v ss =0v v ina =5vpp sinewave f= 1khz; r l = 10k w 6 feedthrough channel off feed.=20log (v out / v ina ) fdt -50 db all switches off; v ina = 5vpp sinewave f= 1mhz; r l = 1k w . v dc =5v 7 crosstalk between any two channels for switches li - ji and lj - jj. li - ji is on lj - jj is off xtalk=20log (v jj /v li ). x talk -40 -90 db db v ina =2vpp sinewave f= 1.0mhz; r l = 600 w . v ina =2vpp sinewave f= 3.4khz; r l = 600 w . v dc = 5v 8 propagation delay through switch t ps 10 ns c l =50pf ac electrical characteristics ? - control and i/o timings - voltages are with respect to v ss =v ee =0v unless otherwise stated. characteristics sym min typ ? max units test conditions 1 digital input capacitance c di 5pfv dd =10v 2 setup time d0-d3 to ae t ds 150 200 ns ns v dd =10v v dd =5v 3 hold time d0-d3 to ae t dh 120 300 ns ns v dd =10v v dd =5v 4 setup time address to ae t as 0 50 ns ns v dd =10v v dd =5v 5 hold time address to ae t ah 120 300 ns ns v dd =10v v dd =5v 6 ae pulse width t aew 100 250 ns ns v dd =10v v dd =5v 7 ae to switch status delay t pae 200 650 300 900 ns ns v dd =10v v dd =5v 8 data to switch status delay t plh t phl 250 650 400 1000 ns ns v dd =10v v dd =5v 9 mr to switch status delay t mr t mrr 250 500 200 500 400 600 350 750 ns ns ns ns v dd =10v v dd =5v v dd =10v v dd =5v see note 1 see note 1 see note 2
MT8804a cmos 3-8 figure 6 - control memory timing diagram table 1 - address decode truth table notes: 0 - low logic level 1 - high logic level x - dont care condition + - indicates connection between junctor and addressed line ? - indicates no connection between junctor and addressed line memory reset mr address enable ae address addressed line input data to control memory junctors connected to addressed line a2 a1 a0 d3 d2 d1 d0 j3 j2 j1 j0 1 x x x x all x x x x all switches "off" 0 0 x x x none x x x x no change of state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 l0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? ? ? ? ? ? ? ? + + + + + + + + ? ? ? ? + + + + ? ? ? ? + + + + ? ? + + ? ? + + ? ? + + ? ? + + ? + ? + ? + ? + ? + ? + ? + ? + 0 0 1 1 0 0 0 0 1 1 l1 l1 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 0 0 1 1 0 0 l2 l2 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 0 0 1 1 1 1 l3 l3 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 1 1 0 0 0 0 l4 l4 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 1 1 0 0 1 1 l5 l5 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 1 1 1 1 0 0 l6 l6 0 1 0 1 0 1 0 1 ? + ? + ? + ? + 0 0 1 1 1 1 1 1 1 1 l7 l7 0 1 0 1 0 1 0 1 ? + ? + ? + ? + t aew t as t dh t plh /t phl t pae t mr t mrr t plh /t phl t ds t ah 50% 50% 50% 50% 50% 50% 50% 50% 50% mr ae address d0-d3 switch on off
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